The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to a semiconductor device with an electrode of conductor embedded within a connecting hole formed in an insulating film formed on a semiconductor substrate and method of manufacturing it.
With development of high-integration of a semiconductor device, the width of an internal wiring and size of a connecting hole of the semiconductor device has been reduced. Conventionally, in order to connect an upper wiring and a lower wiring or a semiconductor substrate electrically through a minute connecting hole, a plug technique in which a metallic film is selectively formed within the connecting hole has been generally adopted. Since the metallic film formed by the sputtering is difficult to provide sufficient coating, in the plug technique, the refractory metallic film of e.g. W formed by the CVD technique is etched back to form a metallic film within the connecting hole.
Now, referring to FIGS. 14 to 18, an explanation will be given of a semiconductor device and its manufacturing method using the above plug technique.
First, as shown in FIG. 14, on a semiconductor substrate 51 formed are an oxide film 52 for element isolation, a gate electrode 53 and source/drain regions 54a-54e of a transistor and a first interlayer insulating film 55. A first connecting hole 56 passing through the source/drain region 54b is formed in the first interlayer insulating film 55. Thereafter, a metallic film is formed on the surface of the first interlayer insulating film 55 and embedded within the interior of the first connecting hole 56. The metallic film is subjected to photolithography and etching treatment to form a first wiring layer 57.
As shown in FIG. 15, after a second interlayer insulating film 58 is formed to cover the first wiring layer 57, a second connecting hole 59 is formed which passes through the second interlayer insulating film 58 to reach the source/drain regions 54a and 54c. The entire surface is coated with a polysilicon layer which is in turn subjected to the photolithography and etching treatment to form a charge storage node (hereinafter referred to xe2x80x9cstorage nodexe2x80x9d) 60. A third insulating film 61 is formed on the entire surface so that it is thin, and is coated with a polysilicon layer again which is subjected to the photolithography and etching treatment to form an upper electrode 62 for charge storage (hereinafter referred to as xe2x80x9ccell platexe2x80x9d). The storage node 60, third insulating film 61 and cell plate 62 constitute a capacitor element. The quantity of storable charges is proportional to the surface area of the storage node 60 and inversely proportional to the film thickness of the third insulating film 61. However, since a finer element leads to a smaller size of the storage node 60, generally, contrivance such as low-profiling the third insulating film 61 and greatly changing the height of the storage node 60 is made to assure the quantity of storable charges.
Referring to FIG. 16, after a fourth interlayer insulating film 63 and a fifth interlayer insulating film 64 are formed so as to cover the cell plate 62, a third connecting hole 65 is formed which passes through the fifth interlayer film 64, fourth interlayer insulating film 63, second interlayer insulating film 58 and first interlayer insulating film 55 in a peripheral circuit area to reach the source/drain region 54d, 54e of the transistor.
In this case, since the storage node 60 is formed in a memory cell area, a large surface step or level difference is formed between the memory cell region and the peripheral circuit region. The surface step that is greater than the focusing depth in the photolithography may lead to poor resolution of a resist pattern.
In addition, the etch back treatment of the metallic film may generate the remainder of the refractory metal at the step which is a cause of electrical short-circuiting.
In order to relax such a problem which becomes serious with an increase in the height of the storage node 60, the fourth interlayer insulating film 63 is generally subjected to a flattening technique using BPSG (Boro-Phospho Silicate Glass).
The BPSG film is softened at a high temperature of 800xc2x0 C. or higher to provide a smooth flow shape in the surface, thereby reducing the surface step. The flatness depends on the concentration of B (boron) or P (phosphorus) and becomes more excellent with an increase in the concentration. As the case may be, the surface of the fourth interlayer insulating film 63 is polished by the CMP (Chemical-Mechanical-Polishing) to improve the flatness of the surface.
Referring to FIG. 17, a first refractory metallic layer 66 and a second refractory metallic layer 67 are formed so as to cover the interior of the third connecting hole 65 and the surface of the fifth interlayer insulating film 64. The first refractory metallic layer 66 and second refractory metallic layer 67 maybe made of generally Ti, W or its nitride, silicide, etc. Further, the first refractory metallic layer 66 and second refractory metallic layer 67 on the fifth interlayer insulating film 64 are etched away to form a metallic plug 68 composed of the first refractory metallic layer 66 and the second refractory metallic layer 67 only within the third connecting hole 65.
Thereafter, a metallic film 69, made of an aluminum alloy such as AlSi, AlSiCu, AlCu, etc. and an antireflective film 70 are formed so as to cover the fifth interlayer insulating film 64 and the metallic plug 68. They are subjected to the photolithography and etching treatment to form a second wiring layer 71. The aluminum alloy, which has a high surface reflection coefficient, is difficult to form a resist pattern through the photolithography. For this reason, the antireflective film 70 is formed on the metallic film 69. The antireflective film 70 may be a refractory metallic film made of TiN, Wsi, MoSi, TiW and W, etc. or their compound. The antireflective film 70 serves to reduce the surface reflection coefficient of the aluminum alloy and improve the reliability by reinforcement of the mechanical strength.
FIG. 18 is an enlarged view of an area xe2x80x9cAxe2x80x9d in FIG. 17. As seen from FIG. 18, in a conventional semiconductor device, the metallic film 69 is deposited by sputtering. Therefore, the coating of the metallic film 69 may deteriorate and break in the recess of the metallic plug 68 (step formed between the fifth interlayer insulating film 64 and the surface of the metallic plug 68). The aspect ratio of the recess portion (ratio of the recess height to the size of the connecting hole) increases with a reduction in the size of the connecting hole so that the coating of the metallic film at the step deteriorates. Therefore, this problem becomes serious with miniaturization of the semiconductor device.
As a technique for solving the problem, for example, JP-A-7-288244 and JP-A-9-167797 disclose a technique for canceling the step (level difference) using the CMP (Chemical Mechanical Polishing) after a conductive layer has been formed. This CMP technique can reduce the recess in a method of forming a conductive plug, and hence can obviate the problem of the plug forming method by RIE (Reactive Ion Etching).
However, the above technique using the CMP additionally requires a polishing apparatus or an apparatus for cleaning a wafer after the polishing, and also presents a problem of complicating a manufacturing process that the surface of the insulating film where a connecting hole is to be formed must be flattened through the CMP.
Other techniques have been also proposed. One is to improve the coating of the metallic film by depositing it at a high temperature of 400xc2x0 C. to 500xc2x0 C. by sputtering (high temperature sputtering) . The other is to cause the re-flow of the metallic film at a high temperature of 400xc2x0 C. to 500xc2x0 C. after it has been deposited by ordinary sputtering (reflow sputtering).
These techniques can dramatically improve the coating at the plug recess. However, all these techniques require for the sputtering apparatus to be modified so as to endure a high temperature, and present a problem that the film surface becomes uneven severely owing to the grain of the metallic film according to the cooling condition after a high temperature has been held and hence the production yield due to the remainder of etching deteriorates.
As a technique for reducing the plug recess without adopting the CMP, for example, JP-A-2-45934 and JP-A-8-250590 discloses a technique of etching the insulating film after the plug has been formed, thereby removing the plug recess. However, where the insulating film is etched back by the dry etching disclosed in JP-A-2-45934, F, C, O, etc. contained in the etching gas will be adsorbed onto the surface of the conductive plug to form a deteriorated film. This makes unstable the contact resistance between the plug and overlying wiring.
The present invention has been accomplished in order to solve the problems involved in the conventional semiconductor device described above and its manufacturing method. An object of the invention is to improve the step coating of a metallic film at a recess using a conventional semiconductor manufacturing apparatus without complicating the manufacturing process, thereby provide a reliable semiconductor device and its manufacturing method.
The semiconductor device according to the invention is a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising:
a first insulating film; a second insulating film formed on the first insulating film;
a conductive plug embedded within an connecting hole which passes through the first and the second insulating film;
a wiring layer formed on the second insulating film so that it is communicated with the conductive plug, wherein the conductive plug protrudes from a surface of the insulating film, and the connecting hole is shaped so that its opening has a larger diameter at its upper position.
Further, the semiconductor device according to the invention is a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising:
a first insulating film;
an etching stopper film formed on the first insulating film;
a conductive plug embedded within a first connecting hole which passes through the first insulating film and the etching stopper film;
a wiring layer formed on the etching stopper film so that it is communicated with the conductive plug, wherein the conductive plug protrudes from a surface of the etching stopper film.
Furthermore, the semiconductor device according to the invention is a semiconductor device further comprising a second insulating film formed on the etching stopper film, wherein the wiring layer is embedded with a second connecting hole and has a thickness approximately equal to that of the second insulating film.
Further, the semiconductor device according to the invention is a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising:
a first insulating film;
an etching stopper film formed on the first insulating film;
a first conductive plug embedded within a first connecting hole which passes through the first insulating film and the etching stopper film; and
a second conductive plug formed in a second insulating film formed on the etching stopper film so that it is communicated with the first conductive plug, wherein the first conductive plug protrudes from a surface of the etching stopper.
Furthermore, the semiconductor device according to the invention is a semiconductor device wherein the first insulating film is an oxide film and the etching stopper film is a nitride film.
Further, the method of manufacturing a semiconductor device according to the invention is a method of manufacturing a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising the steps of:
forming a first insulating film on the substrate;
forming a second insulating film on the first insulating film;
forming a connecting hole which passes through the first and the second insulating film;
forming a conductive film within the connection hole and on a surface of the second insulating film and etching back the conductive film until the second insulating film is exposed, thereby forming a conductive plug within the connecting hole;
etching back the second insulating film by dry etching;
exposing surfaces of the second insulating layer and the conductive plug to plasma atmosphere containing oxygen, cleaning them by argon sputter etching or irradiating them with UV light so that impurities on the exposed surfaces of the second insulating film and the conductive plug are removed; and
forming a wiring layer on the second insulating film so that it is communicated with the conductive plug.
Furthermore, the method of manufacturing a semiconductor device according to the invention is a method of manufacturing a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising the steps of:
forming a first insulating film on the substrate;
forming a second insulating film on the insulating film;
forming a connecting hole which passes through the first and the second insulating film;
forming a conductive film within the connection hole and on a surface of the second insulating film and etching back the conductive film until the second insulating film is exposed, thereby forming a conductive plug within the connecting hole;
etching the insulating film using an HF dilute solution; and
forming a wiring layer on the second insulating film so that it is communicated with the conductive plug.
Further, the method of manufacturing a semiconductor device according to the invention is a method of manufacturing a semiconductor device having a wiring structure including a conductive plug which passes through an insulating film on a substrate, comprising the steps of:
forming a first insulating film on the substrate;
forming an etching stopper film on the first insulating film;
forming a second insulating film on the etching stopper film;
forming a connecting hole which passes through the first insulating film, the etching stopper film and the second insulating film;
forming a conductive film within the connecting hole and on a surface of the second insulating film and etching back the conductive film until the second insulating film is exposed, thereby forming a conductive plug within the connecting hole;
removing the second insulating film until a surface of the etching stopper film is exposed; and
forming a wiring layer on the etching stopper film so that it is communicated with the conductive plug.